Voltage comparison circuit



Sept. l0, 1963 l. M. SHEAFFER, JR., ETAL VOLTAGE COMPARISON CIRCUIT Filed Jan. 29, 1959 2 Sheets-Sheet 1 READ SIGNAL TAPS) INVERTED slGNAL TAPs/ INVENToRs ISAAC M. SHEAFFERJR BY ERIC sElF F /g. 3

iQ/b. 5.

AGENT l. .sHEAFF|-:R, JR., ETAL 3,103,646

VOLTAGE COMPARISON CIRCUIT Sept. 10, 1963 2 Sheets-Sheet 2 Filed Jan. 29, 1959 AGENT United States Patent O 3,103,646 VOLTAGE COMPARISON CIRCUIT v Isaac M. Shealer, Jr., Berwyn, and- Eric Seif, Philadelphia, Pa., assignors to Burroughs Corporation, Detroit, Mich., a corporation of Michigan Filed Jan. 29, 1959, Ser. No. 789,983 17 Claims. (Cl. S40-146.3)

moans Patented Sept. 10, 1963 from the-taps are passed to a plurality of correlation networks, with one network assigned to each character or A to elect proper signal summations.

In the art of character recognition there has been inare printed is then transported past a magnetizing station Where the magnetizable ink is subjected to a magnetic eld in order to magnetize the ink land, consequently, the symbols. The symbols, having thus been magnetized, are characterized by their own magnetic eld which provides a basis for recognizing or read-ing these symbols.

A known method for reading these magnetized symbols includes a magnetic reading transducer head which intercepts the magnetic fields of the respective symbols and provides characteristic voltage output signals respectively for each symbol. According to its particular shape, any symbol will provide greater or lesser amounts of magne-tic iiux distributed along the character since the quantity of flux available is directly proportional to the inked area which has been magnetized. For instance, the numeral 8, having been magnetized, would provide a greater amount of flux at the leading and trailing edges than would be provided in the center portion. The voltage signal supplied by the transducer is proportional to the time rate of change of linx; therefore, each of the characters provides a distinct voltage signal related to their respective shaps. Each varying voltage signal or waveform, as may be depicted on a cathode ray tube for the entire transport of the symbol under the head, is characteristic of the associated symbol which is being passed under the transducer head. The varying voltage is dynamically stored for use so that :at the end of the signal, the symbol which it represents may be recognized electronically in the Way an observer might identity the symbol by observing the still picture of the voltage waveform on a cathode ray tube.

In order to store this varying signal dynamically and provide an instantaneous still picture of the symbols characteristic voltage waveform, a del-ay line is used. The symbol is time-divided into seven sections along the direction of document transport. The signal from the transducer, after proper amplification and liltering (lowpass) is fed to la delay line which, in turn, has eight taps which define the above-mentioned sections. The time necessary for the signal to pass through the delay line is synchronized with the time which transpires lor a scanning operation of the symbol by the head. The speed of the document is, obviously, the controlling factor. In accordance with this arrangement, at the time that the beginning of the signal, representing the leading edge oi the printed symbol being read, appears at the last tap of the delay line, the end of the signal, representing .the trailing edge ot' the printed symbol, appears -at the lirst tap, or some tap between the lirst and the last if the symbol is relatively narrow in width, for example, the numeral one. Hence, at each tap there appears a voltage value which, if plotted graphically, would represent a characteristic voltage waveform for the symbol being read.

In the character recognition arrangement with which the present invention is primarily considered, the signals The provision of a diierent correlation network lfor each symbol should provide at sampling time a single maximum significant output, thereby to identify the particular character being read. In practice, howevenut has been lfound that because of the noise or spurious signals which are spawned in the system, there are times when more than one channel has a signal which so closely approximates the highes ofthe signals being compared that the machine receives the false indication that more than one character has been read by the reading head. It is imperative that the machine recognize this more than one'character has been read by the reading situation and provide an alarm or a reject signal in response to which the document would be specially handled. Such recognition is desirable because, under this last-mentioned condition, the highest signal may represent a character which is not truly being read and if the system is operating properly two or more such signals should not appear.

It follows, then, that a voltage comparison circuit forv It is a further object to provide a voltage waveform Y comparison circuit which will be nonresponsive to each channel input signal excepting any channel signal, whose value is higher than a predetermined percentageof the highest yinput signal including the channel with the Ithigh'- est input signal. l K

In accordance'with a main feature of the present invention, each of the channel signals is fed to a mixer,v

whose output, in turn, is proportional to that off the highest input signal, and which output is fed to a feedback amplifier. The feedback amplifier has a lixed gain which provides an output Whichis a predetermined percentage of the highest channel input signal and which is yinverted and returned to each channel input, thereby rendering each input channel relatively negative unless such channels input signal is higher than said predetermined percen-tage of the highest channel inputsignal.

In accordance with another feature of the presentinvention, each of the input channels mentioned above is connected to an output circuit which is responsive to any channel whichk has a realti'vely positive value at a predetermined sampling time, thereby recognizing the highest channel input which thus identfies the character being read and providing a basis for reception if more than one channel input is relatively/positive.

' Ihe foregoing and other objects and features of invention will be best understood by reference to the following description of a preferred embodiment of the invention taken in conjunction with the accompanying FIG. 2 is a schematic diagram of a portion of a character recognition system including the circuit of the present invention;

FIG. 3 shows the ux linking the read head as it passes over certain characters, and the voltage generated in re'-` sponse to the llux linkage. i

Referring to FIG. 1, there are found three voltage signal terminals, 11, 12 and 13, respectively, representing a rst channel, a second channel, and an nth channel. The function of the circuit shown in FIG. 1 is to cornpare the yvoltages appearing at the terminals 11, 12. and 13, and after such comparison, to indicate which terminal has `the highest voltage. The indication is accomplished by the illumination of whichever of the indicating lights 14, 15 o r 1 6 is associated with the terminal where the highest signal is appearing. The Vcircuit operation, which will be described in detail hereinafter, pro vides, however, that `if any of the input signals to be compared has a value greater than Moths of the value of the highest signal being compared, then the panticular channels where such greater than D/oths valued signals appear will have their associated lights illuminated, in addition tothe light which represents the highest channel. Assume that at terminal e1 there appears a voltage value of volts, while at e2 there appears a voltage value of 8 volts, and at e,L1 there appears a value of 9.5 volts. Ac-

cording to the system operation described above, theY lights y14, and 16 should be illuminated lwhile the light should not be so illuminated. The feedback operation which occurs as soon as the voltages are applied to the terminals 11, |12 and 13 returns a voltage signal to the bus 17 which is proportional to Moths of the highest voltage value applied at any one of the terminals and of opposite polarity. The reject value, chosen as loths, dictates that if a signal on any channel is more than %0tbs of the highest signal being compared this will give rise to the systems rejecting that particular reading since either channel might b e correct. This reject is accomplished by providing an amplifier 18 which has a stable fixed gain of minus 18 relative to its input and resistors in the feedback loop equal to the effective resistance of the associated input channel. It will become apparent later `that a gain of minus 18 is necessary to accomplish this feedback signal of minus` *Moths value of the highest input signal. -If some reject level other 'than iMoths is to be used in a system, then the amplier may have some other fixed gain depending on the resistor values in the feedback loop. The amplifier 18 can be. any D.C. operational amplier which has a stable fixed gain.

Consider now 4the determination of the voltage to. be

applied at point -19 in order to accomplish a i)oths re-` ject level. The resistors 20 and Z1 are` chosen to be equal, thereby making the voltage at point 2,2 equal to` where Ae is the voltage difference measured between points 11 and 19,. By selection, the butler amplifiers 24, 31 and 432 have a gain of 1 and the larnps4 14, 15 and 16 are rendered conducting with a control voltage higher than zero. Therefore, a zero or ground potential applied at point` 2`2 will not provide a positive potential at point 23, to illuminate the lamp 14. It will be seen that if Ae should equal 2e1, then the point 22 would be zero and lthere. Iwould be no illumination of the light 14; and Ae becomes equal to 2e1 when the voltage applied to the point- 19 equals the voltage applied to the point r11. It follows that ifthe voltage applied to` point 1,9` is minus loths of the highest voltage at any ofthe terminals, anda signal which is equal to %0ths ofV the highest voltage applied appears at :the terminal 1-1, this voltage would not cause the buifer amplifier 24 to conduct. However, a signal which is more than the lyloths value, if applied to the terminal 11, `would cause the buffer amplifier Z4 to conduct, thereby illuminating the light 14. In fthe illustration, the highest signal is applied to the point 11. As suggested before, the voltage at point 22 is equal to and Ae equals 1.9 eh (where eh=e highest) when measured between the highest input terminal signal and the common connection 17; therefore, the junction point between the resistors equals .OSeh since the resistors are equal. This voltage .05ct1 is the controlling voltage at `the mixer output point 33 since the mixer 34 operates in a manner similar to a standard OR gate. This provides an input to the amplifier 18 which is always proportional to and controlled by the highest voltage being compared. To provide a voltage value on the common connection 17 equal to minus mths eh the gain (K) of the amplifier 118 must be lixed according to (K) (.05eh)=.9eh. It becomes obvious, then, that (K), the amplification of the ampliier 18, must be equal to minus 18. If Ae equals 1.9e1, which would be the case in our illustrative example, then the voltage appearing at point 22 would be equal to 0.05,e1. The positive voltage .05e1 appearing at point 2,2 would cause the buffer amplifier 24 to provide a posi-` tive signal of 0.05e1 at 23 and thereby illuminate the light y14. i

With respect to FIG. 1, a more strict proof can be considered for the general case: e1, e2, 2l are equivalent `output voltages of the correlation networks. Consider that e1 e2, e1 e. R is the equivalent impedance of any correlation network and R1 is the feedback loop resistor (21, Z3, 3,0) for any channel.

The current summations at three summing points:

1 en 01(en Cri-C261) -to show similarity add to each side of the Equation 7 the term and fixed fractions so that K=l8 and the proportionality constant This analysis, if considered with the circuit of FIG. 1, assumes that the buffer amplifiers 24, 3-1 and 32 have a gain of l and perfect peak detection at the input of arnplifier 18. Deviation from these assumptions does not change the basic principle of operation.

The reject value of %ths is an arbitrary figure and, depending upon the requisites of the system, some other percentage can be chosen. In the preferred embodiment with which the present inventive circuit is principally considered, lthe reject value, or the value over ywhich a signal will give rise to a reject condition, is syloths of highest value of any one of the plurality of applied input signals.

According to our illustrative example, in which e121() volts, e2=8 volts and en=9.5 volts, by voltage divider considerations and as discussed above, there appears at point 22, volts; at point 25, -0.5 volts; and at point 26, +0.25 volts. The resistors 20, 2,1, and 27 through 30 all have identical values. The resistors 20, 2.7 and 29 represent the equivalent internal resistance of the input circuits or the correlation circuits, as will be described below. It follows, in our example, that with a +0.5 volts appearing at point 22, the indicator light 14 is turned on; with the voltage value of -0.5 volts appearing at point 25, the buffer amplifier 3l has a negative output and, therefore, the lamp 15 is not illuminated, while with the +0.25 volts appearing at point 26, the buffer amplifier 32 has a positive output voltage to turn on the lamp 16. The buffer amplifiers '24, 3l and 32 in the preferred embodiment are of the emitter-follower type, although any fixed voltage gain amplifier device which provides, at the respective points 22, 25 and 26, and at the output of the buffer amplifier, a voltage value which will control current flow through the associated lamps, would be acceptable.

In FIG. 2 there is shown a portion of a character recognition system with the basic circuitry of FIG. 1 included. It will be noted that for the correlation networks 37, 38 and 39, representative values for the resistors therein have been included. Each `correlation network can be said to define the ideal waveform of the character to which it is assigned. -If the conductance (g) values of the legs of ra particular network are plotted, with the taps on the delay line to which the legs are con'- nected determining the sign of the values, the plotted points can ybe joined to represent graphically the ideal waveform of the character to which the particular network has been assigned. Each network has resistors whose values are weighted such that if the waveform of the character, which the network represents, is present on the tdelay line at sampling time, there is a relative maximum output from the representative correlation network. The output is qualified as relative maximum because it is maximum when compared with all the other correlation network outputs at sampling time. For instance, at sampling time a particular network may have the maximum output at +5 volts since its associated character waveform is on' the Adelay line, tand since all other networks have less than +5 volts output. This same particular network may have at a second sampling time, .a +7 volt output which would not be maximum since, at -a second sampling time, a second waveform is on the delay -line rendering a second network with an output of +10 volts. A reduction to an equivalent resistor of the parallel resistor network for the correlation network 37, and including the standardizing resistor 40, will reveal that the equivalent resistor value, looking back into the last mentioned parallel arrangement, will -be 40.2K, where K: r-ilohms. In the preferred embodiment, each correlation network, including its associated standardizing resistor, has an equivalent resistor value of 40.2k, although some other value might have been selected. The 40.2k network value was arrived at by design considerations, in particular, the conductance (g) values Iof the various correlation networks to represent the ideal waveforms, the frequency range of the signal-s in the system, the 4load effect on the del-ay line, and the distributed capacitance established by the circuitry. As was suggested in connection with the description of FIG. l, the resistors 20, 27 and 29, represent respectively the equivalent internal resistances as seen by looking back 4into the vparallel arrangements of the correlation resistor networks and the standardizing resistor.

For a lbetter understanding of the operation land utility of the circuit, FIG. 3 should be considered in connection with FIG. 2. In FIG. 3, there are shown rthe printed figures of the numerals zero, two and four, which are designated respectively 4l, 46 :and 47. These numerals are formed in accordance vwith standard characters accepted by the American Bankers Association .and designated as E13/B characters. Directly below the numeral 0, there is shown la waveform 42 which depicts the flux values related to time which will tbe sensed by the reading head. In the waveform 42, the solid line represents the ideal flux linkage with the read head, while the dotted wlaveform more closely represents the actual linkage of the flux with the read head. Below the waveform 42, there is shown the waveform 43 which represents the induced voltage in the read head winding related to time. The waveform 43 is superimposed upon a delay line 44 which, in turn', has Read Signal Taps and Inverted Signal Taps. It may be noted that the `delay line 44 appears in FIG. 2 as fa dual polarity `delay line 45, 'and the taps which are shown to define the sections in connection with the "0 numeral 41 are identical with the taps on the dual polarity delay line 45 of FIG. 2. In FIG. 3, the printed numerals 2 and 4 are designated 46 and 47 with their respective flux waveforms 4S and 49, and their voltage output waveforms respectively 50 and 51. It is to lbe understood that the printed figures, such as the numerals 0, 2 and 4 of FIG. 3 are scanned from right to left, that is, the 'documents are transported under the read head moving from left to right, so that the right hand edge of the numeral is scanned rst. This is more clearly depicted by the direction of time z indicated in the ilux graphs and in the voltage graphs. In accordance with this method of scanning, the zero tap is at the far right hand side of the dual polarity delay line 44, or as shown in the dual polarity delay line 45 of FIG. 2, the zero tap is at the far end from the input of the signal.

The correlation networks shown in FIG. 2 are provided to effect a correlation operation between a signal appearing on the dual polarity idelay line and each stored signal represented by the correlation networks. In other words, each signal which appears on the dual polarity delay line is compared against each stored ideal signal represented vby the selection of the resistors in the correlation, or summation, networks. The design of the correlation networks is n accordance with standard design techniques. According to correlation techniques, the best correlation is going to occur between the actual character waveform signal :appearing on the dual polarity delay line and the stored ideal signal representing this character. A comparison Vbetween any character waveform appearing on the dual polarity delay line and any stored waveform, other than the stored waveform Iassigned to the character, will provide a summation or integrated correlation function output which will be less than -the summation or integrated correlation function output between the character waveform on the delay line and its assigned stored waveform. This in essence, represents an yauto-correlation at the time tau=0.

Consider that in FIG. 2 the read head 52 is scanning a numeral which has been printed with magnetizable ink and magnetized. The signal 43 of FIG. 3 is generated by the read head 52 and is passed through the amplifier l53 to the dna-l polarity delay line 45, as shown by the overlay of waveform 43 on the delay line 44. A set of taps 54 entitled Read Signal Taps is provided to transmit from the delay line a voltage signal according to a vwaveform considered normal as it appears thereon'. A second set of taps 55 entitled Inverted Signal Taps is provided to transmit from the delay line a voltage signal in ian inverted form of the normal waveform, as the latter appears on the taps 54. Examination of FlG. 2 will reveal that the taps which are connected to the correlation network 37 of the numeral "0 Iare the read signal zero tap, the read signal sixth tap, the inverted signal first tap and the inverted signal seventh tap. An examination of FIG. 3 will reveal that the waveform 43 has positive significant values at the zero tap and at the sixth tap, as Well as negative significant values at the first and seventh taps. If these negative voltages lare inverted, as is done in the dual polarity delay line, then the voltages which are passed to the correlation networks 37 are all of positive polarity and there is a signal summation of the four signals thereat.

Further consideration might be given to the reaction of the correlation networks 38 and 39 to the waveform 43 appearing on the delay line. It will be noted that the resistors of the correlation network 38 representing the numeral 2 are respectively coupled to the read signal zero and third taps, and to the inverted signal first, fourth and fifth taps. In FIG. 3 an examination of the voltage time graph 43 under the numeral 50 will reveal that the waveform 43 does have signicant voltage values at zero tap time and the rst tap time, but has no signiiicant voltage values :for the third, fourth or fth taps. It then follows that the correlation network representing the numeral 2 will have `a summation of the two voltage values, those appearing at the zero tap and at the iirst tap, but these voltage values, when summed, will have a value less than the summation of the four voltages which -are added `in the correlation network representing the numeral "0 as described above.

Further examination reveals that the correlation network 39, representing the numeral "4" has its respective resistors coupled to the read signal zero and fourth taps, and to the inverted signal second, sixth and seventh taps. Consider how the waveform 43 is read by the correlation network 39. We find that at zero tap time the significant voltage of the waveforms 43 is properly read. There are no significant voltage values at the second and fourth taps. At the sixth tap, the voltage value of the waveform 43, which is positive, will be inverted to a negative -value since the network 39 has its connection to the inverted signal side. Thus, the negative output of the sixth tap will have a substrac-ting effect. 'I'he voltage value lat the seventh tap, which inherently has a negative value, is inverted to provide a positice signal as is done with the numeral 0. Obviously the summation value of these -tap voltages appearing at the network 39 will be less than the summation value of the four tap voltages accomplished by the assigned correlation network. Although this last consideration was undertaken with examination and observation of the networks 38 and 39, each of the networks representing the possible characters or numerals to be read in the system will provide a similar operation, namely, that the correlation network which is assigned to any particular character will provide the highest output when the particular character is on the delay line, said highest output being highest in comparison fto all other correlation network outputs at sampling time.

l-t follows` that the correlation network 37 representing the numeral O will provide the highest output voltage since the numeral 0, in our illustrative example, is the numeral being read, and the waveform 43, therefore, is appearing on the dual polarity delay line. Consequently, ythe -highest signal appears at the point 56, and lesser values or relatively negative potential values appears at the point 57 'through 61. The feedback loop via the buffer amplifiers 62 through 67, and the fixed gain inverter amplifier 68, operates as described in conjunction with the circuit shown in FIG. l, to render each of the points 57 -through 61 in a relatively negative voltage conduition.

When the leading edge of the signal on the delay line appears at the zero tap, the system is signalled to sample the correlation network outputs. Ihe sampling time signal may be effected simply by providing a threshold device at the zero tap which tires a sampling pulse generator 69 to provide a sampling gate pulse. More sophisticated and desirable methods for providing a sampling pulse, for instance, sampling over `the interval between the zero and first taps, are used in character recognition systems, but are not considered in detail here because such arrangements are not basically related to the presentinvention. The sampling gate pulse is passed along the common connection 70 to each of the gating devices 71 through 76. The gating devices 71 through 76 may be of a number of varieties. For example, a gating device such as an AND gate might be used, or preferably from an engineering standpoint a series-pair switch (a pair of junction transistors whose collectors and `bases are series and common connected) might be used.

The present invention offers decided advantages for limiting the `dynamic range over which components in the system must be chosen or designed to operate satisfaetorily. For instance, in the design consideration of :the

system the noise (including drift) level is established and` concurrently a satisfactory signal-to-noise ratio is set as requisite for the system design. This procedure establishes a minimum required signal amplitude. -In a praetical character recognition system the maximum transducer signal amplitude may be several times the minimum transducer signalamplitude, because of variations in printing intensity, variations in distance between transducer head and document, and variations in the geometry of the various characters. The advantage of lthe present -inventive circuit becomes evident when a known characteristic recognition system is considered wherein differential amplifiers are used to effect a comparison between the output signals of the individual correlation networks and a standard signal. The gain of these or any amplifiers in the system is established by the above mentioned minimum required signal amplitude. As suggested above, the transducer signal may have a maximum amplitude several times that of the minimum transducer signal for the reasons given above. Since the transducer signal can be considered substantially uncontrolled but having known limits, the dynamic range lof the amplifiers must be large to handle the maximum signals passing therethrough. Amplifiers, which must operate linearly over fa large dynamic range, Iof course, are critical in design and costly. The feedback loop of the present invention in effect reduces the amplitudes of the input signal to the mixer, thus sharply reducing the requisite dynamic range for the various components, such as the buffer amplifiers. In view of the above discussion the present invention is clearly desirable and advantageous.

While we have described above the principles .of our invention in connection with specific apparatus, it is to be vclearly understood that this :description is made only by -way of example and not as a l-imitation to the scope of our invention as. set lforth in the objects thereof and in the accompanying claims.

What is claimed is:

1. A voltage comparison circuit .for comparing a plurality of voltage signals and detecting each of said voltage signals whose valve is greater than a predetermined percen-tage of the highest voltage signal compared, comprising, a plurality of voltage signal sources providing si-gnals -to be compared, signaly m-ixer means having a plurality of input means, each of said input means coupled respectively to Ian associated one of said plurality of voltage signal sources, amplifier means providing an output signal which is a fixed amplification of an input signal applied thereto, said amplifier means coupled to accept said mixing means output signal and provide said fixed amplification thereof, feedback circuitry means coupled between said amplifier output and each of said inpu-t means, said Afeedback circuitry in conjunction with said amplifier output signal and the respective voltage signal sources providing respectively at each of said input means a summation signal, each of said voltage signal sources -whose value is greater than a predetermined percent-age of the highest voltagesignal compared causing an indicative summation signal to appear at its associated input means, and utility means coupled to each of said mixer input means to |be responsive to an indicative summation signal thereat.

2. A voltage comparison circuit for comparing a plurality of voltage signals and detecting each of said voltage signals whose value is grea-ter than a predetermined percentage of the highest voltage signal compared, cornprising, 'a plurality or" voltage signal sources providing signals to 'be compared, signalmixer means having a plurality of controllable input means, each of said controllable input means coupled respectively tol an associated one of said plurality of voltage signal sources, amplifier means providing an ou-tput signal which is a fixed amplification of an input signal applied thereto, said amplifier means coupled to accept said mixing means output signal and to provide said fixed amplification thereof, feedn back circuitry means `coupled between said amplifier output and each of said controllable input means to provide in conjunction with said amplifier output signal and the respective voltage sign-al sources a controlling signal at each of said controllable input means, said respective controlling si-gnals causing each of said `controllable input means which is coupled to an associated voltage source whose value is greater than said predetermined percentage of thehighest voltage signal compared to provide an indication signal output therefrom and Ifurther causing each controllable input means which is coupled to an associated voltage source whose value is Aless than said predeter mined percentage to provide a non-indicative signal output therefrom, and utility means coupled to each of said controllable input means to be responsive to said indicative signals.

3. A volta-ge comparison circuit -for comparing a plurality of `voltage signals and detecting each of said voltage signals whose value is greater than a predetermined percentage of the highest voltage si-gnal compared, cornprisin-g, `a plurality of voltage signal sources providing signals to be compared, signal mixer means having a plurality of controllable input means, each of said controllable input means coupled respectively to an associated one of said plurality of voltage signal sources, amplifier means providing fan output signal which is a fixed amplification of an input signal applied thereto, said amplifier means coupled to accept said mixing means output signal and provide said fixed amplification thereof, a plurality of impedances each with first and second ends, each of said first impedance ends respectively coupled to an associated controllable input means, feedback circuitry coupling each of said second impedance ends with said amplier-output, said impedance in conjunction with said amplifier output and the respective voltage sources pro- 'viding a feedback effect to provide an indicativ-e output signal Yfrom each of said controllable input means which is coupled to an associated voltage source whose value is greater than la predetermined percentage of the highest voltage signal compared, and to provide a non-indicative output signal at each controllable input means which .is coupledto an associated voltage source whose value is less than said predetermined percentage and utility means coupled to each of said controllable input means to be responsive to said indicative output signals.

4. A voltage comparison circuit for comparing a plurality of voltage signals and detecting each of said voltage signals Whose value is greater than a predetermined percentage of the highest voltage signals compared, comprising, a plurality of voltage signal sources providing signals to .tbe compared, signal mixer means having a plurality of controlla-ble input means, each of said controllable input means coupled respectively to an Aassociated one of said plurality of voltage signal sources, amplifier means provid-ing lan output signal which is a fixed amplification of an input signal applied thereto, said amplifier means coupled to accept said mixing means output signal and provide an output signal which is said fixed amplification thereof, a pluralityof impedances each with first and second ends, each of said `first impedance ends respectively coupled to an associated controllable input means, feedback circuitry coupling each of said second impedance ends with said amplifier output, said impedances in conjunction with said amplifier output and said respective voltage sources providing a feedback effect to provide at each of said impedance second ends a signal which is a predetermined percentage of the highest signal applied, thereby `causing an indicative output signal from each of said controllable input means which is coupled to an associated voltage source whose value is greater than a predetermined percentage of the highest voltage signal compared and causing a non-indicative output signal from each controllable input means which is coupled to an associated voltage source Whose value is less than `said predetermined percentage, and utility means coupled to each of said controllable input means to be responsive to said indicative output signals.

5. A voltage comparison circuit for comparing a plurality of voltage signals and detecting each of said voltage signals Whose value is greater than a predetermined percentage of the highest voltage signal compared, comprising, -a plurality of voltage signal sources providing signals to be compared, signal mixer means having a plurality of controllable input means, said signal mixer means providing an output which is proportional to the highest signal applied thereto, each of said controllable input means coupled respectively to an associated one of said plurality or voltage signal sources, amplifier means providing an output signal which is a fixed amplification of an input signal applied thereto, said amplfiier means coupled to accept said mixing means output sign-al and provide an output signal which is said fixed amplification thereof, a plurality of impedances with first and second ends, each of said first impedance ends respectively coupled to an associated controllable input means, feedback circuitry coupling each of said second impedance ends with said amplifier output, said impedances in conjunction with said amplifier output and the respective voltage sources providing a feedback effect to provide an indicative output signal from each of said controllable input means which is coupled to an associated voltage source whose value is 4greater than a predetermined percentage of the highest voltage signal compared, and provide a non-indicative output signal from each controllable input means which is coupled to an associated voltage source whose value is less than predetermined percentage, and indicating means coupled to each of said controllable input means to respectively indicate the presence of an indicative output signal.

6. In -a character recognition system a voltage comparator circuit to detect the various voltage patterns of possible characers to he read comprising a magnetic reading head, signal delay means having a plurality of output taps and input means coupled to said magnetic reading head, a plurality of signal adding networks with one each assigned to a particular character to be read, each of said networks being coupled to a selected plurality of said taps such that for any character read the signal appearing at the output of the network assigned to such character is a greater signal value than any signal appearing at the output of any other network, signal mixer means having a plurality of controllable input means, each' of said controllable input means coupled respectively to an associated one of said plurality of signal adding networks, amplifier means providing an output signal which is a fixed amplification of a signal applied thereto, said amplifier means coupled to accept said mixer means output to provide said fixed amplification thereof, feedback circuitry means coupling said amplifier output to said plurality of adding networks to provide a reference volt-age thereto, said adding network circuitry in conjunction with said reference voltage providing controlling voltages to each of said input means, said controlling voltages providing an indicative output signal at each input means which is coupled to an associated voltage source whose value is greater than a predetermined percentage of the highest signal compared and providing a non-indicative output signal at each input means which is coupled to an associated voltage source whose value is less than said predetermined percentage value, and utility means coupled to each of said controllable input means to -be responsive to each of said input means which provides an indicative signal, thereby to detect a possible character being read.

7. In a character recognition system a voltage comparison circuit according to claim 6 wherein each of said adding networks is a resistor network wherein the respective conductance values of the resistors are proportional to selected ordinate values of the ideal waveform of the character which said respective network represents.

8. In a character recognition system a voltage comparison circuit according to claim 6 wherein said mixer means provides -an output which is proportional to the highest signal applied thereto and wherein each of said controllable means includes a 'buffer amplifier device having a fixed gain.

9. In a character recognition system a voltage comparison circuit to detect the various voltage patterns of possible characters lto be read, comprising a magnetic reading head, signal delay means having a plurality of output taps and input means coupled to said magnetic reading head, a plurality of signal addi-ng networks with one each assigned to a particular character to be read, each of said adding networks having resistor legs whose respective conductance values are proportional to selected ordinate values of the ideal waveform ofthe particular character to which said network is assigned, each of said networks being coupled to a selected plurality of taps such that -for any character read the signal appearing 4at the output of the network assigned to such character has a greater signal value than any signal appearing at the output of any other network, signal mixer means having a plurality of controllable input means, each of said controllable input means coupled respectively to an associated one of said signal adding networks, each of said signal adding networks having an equal equivalent resistance value, amplifier means providing an output signal which is a fixed amplification of a signal applied thereto, said `amplifier means coupled to accept said mixer means output to provide said fixed amplification thereof, a plurality of resistors each of whose value is equal to said equal equivalent resistance value, feedback circuitry means coupling said amplifier output respectively through an associated one of said resistors to said adding networks to provide a voltage divider circuit and a reference voltage thereto, said voltage divider circuitry in conjunction with said reference voltage providing controlling voltages which in turn provide an indicative output signal at each input means -which is coupled to an .associated signal adding network whose output signal is .the highest or greater than a predetermined percentage of the highest network signal compared and which provides a non-indica-tive output signal from each input means which is coupled to an associated signal adding network whose output signal is less than said predetermined percentage value, and utility means coupled to each of said controllable input means to be responsive to each of said input means having an indicative output signal Ithereby enabling the detection of a possible character being read.

l0. In a character recognition system a voltage comparison circuit according to claim 9 iwherein said predetermined percentage is fyloths ofthe highest signal being compared.

11. `In a character recognition system a voltage comparison circuit according to claim 9 wherein said signal delay means includes a dual polarity delay line from whence the signal appearing thereon can be sensed simultaneously in a first form land in an inverted `form of said first tor-m.

12. II-n a character recognition system a voltage comparator circuit to detect the various voltage patterns of possible characters to be read comprising a reading head, signal delay means having a plurality of output taps and input means coupled to said reading head, a plurality of signal adding networks with one each assigned to a particular character to be read, each of said networks being coupled to a selected plurality of said taps such that yfor any character read the signal appearing at the output of the network assigned to such character is a greater signal value than any signal appearing .at the output of any other network, signal mixer means having a plurali-ty of controllable input means, each of said controllable input means coupled respectively to an associated one of said plurality of signal adding networks, amplifier means providing an output signal which is a iixed amplification of a signal applied Ithereto, said ampl-ifier means coupled to accept said mixer means output tto provide said fixed amplification thereof, feedback circuitry means coupling said amplifier output to said plurality of adding networks to provide a reference voltage thereto, said adding network circuitry in conjunction with said reference voltage providing controlling voltages to each of said input means, said controlling voltages providing an indicative output signal at each input means which is coupled tojan associated voltage source whose value is greater than la predetermined percentage of the highest signal compared and providing a non-indicative output signal at each input means which is coupled to an associated voltage source whose value is less than said predetermined percentage value, and utility means coupled to each of said controllable input means tot be responsive to each of said input means which provides an indicative signal, thereby to :detect a possible character being read.

13. In a character recognition system a voltage comparison circuit according to claim `12 wherein each of said adding networks is a resistor network wherein the respective conductance values of the resistors are proportional to selected ordinate values of the idea-l waveform of the character which said respective network represents. l

14. In a character recognition system a voltage comparison circuit according to claim 12 wherein said mixer means provides an output which `is proportional to the highest signal 4,applied thereto and wherein each of said controllable means includes a buier ampliiier device having a iixed gain.

15. In a character recognition system a voltage comparison circuit to detect .the various voltage patterns of possible characters to be read, comprising a reading head, signal delay means having a plurality of output taps and input means coupled to said reading head, a plurality of signal adding networks with one each assigned to` a particular character to be read, each of said adding networks having resistor tlegs whose respective conductance values are proportional to selected ordinate values of fthe ideal waveform of fthe particular character to which said network is assigned, each of said networks being coupled to a selected plurality of taps such that for any character read the signal appearing at the output of the network assigned to such character has a `greater signal value than any signal lappearing at the output of yany other network, signal mixer means having a plurality of controllable input means, each of said controllable input means coupled respectively to `an `associated one of said signal .adding networks, each of said signal `adding networks having an equal equivalent resistance value, amplifier means providing an output signal which is Ia iixed amplification of a signal applied thereto, said ampliiier means coupled viding controlling voltages which in turn provide an indicative output signal at each input means which is coupled to an associated signal adding network whose output signal is the highest or lgreater tha-n a predeterminedr percentage of the highest network signal co-mpared and which provides :a non-indicative output signal from each input means which is coupled to Ian associated signal adding network whose output signal is less than said predetermined percentage value, .and utility means coupled to each of said controllable input means to be responsive to each of said input means having an indicative output signal thereby enabling the detection of a possible character being read.

y16. In a character recognition system a voltage compriso-n circuit according to claim 15 wherein said predetermined percentage is s/wths of the highest signal being compared.

17. ln a character recognition system .a voltage comparison circuit according to claim 15 wherein said signal delay means includes a dual polarity delay line from whence the signal appearing thereon can be sensed simultaneously in a tirst form and in an inverted form of said rst 'formt References Cited in the file of this patent UNITED STATES PATENTS 2,819,397 Davis Ian. 7, 1958 2,860,241 Post Nov. 1l, 1958 2,922,116 Crosby Jan. 19, 1960` 2,924,812 Merritt et al. Feb. 9, 1960 2,927,303 Elbinger Mar. 1, 1960 2,966,672 Horn Dec. 27, 1960 l FOREIGN PATENTS 785,853 Great Britain Nov. 6, 1957 

1. A VOLTAGE COMPARISON CIRCUIT FOR COMPARING A PLURALITY OF VOLTAGE SIGNALS AND DETECTING EACH OF SAID VOLTAGE SIGNALS WHOSE VALVE IS GREATER THAN A PREDETERMINED PERCENTAGE OF THE HIGHEST VOLTAGE SIGNAL COMPARED, COMPRISING, A PLURALITY OF VOLTAGE SIGNAL SOURCES PROVIDING SIGNALS TO BE COMPARED, SIGNAL MIXER MEANS HAVING A PLURALITY OF INPUT MEANS, EACH OF SAID INPUT MEANS COUPLED RESPECTIVELY TO AN ASSOCIATED ONE OF SAID PLURALITY OF VOLTAGE SIGNAL SOURCES, AMPLIFIER MEANS PROVIDING AN OUTPUT SIGNAL WHICH IS A FIXED AMPLIFICATION OF AN INPUT SIGNAL APPLIED THERETO, SAID AMPLIFIER MEANS COUPLED TO ACCEPT SAID MIXING MEANS OUTPUT SIGNAL AND PROVIDE SAID FIXED AMPLIFICATION THEREOF, FEEDBACK CIRCUITRY MEANS COUPLED BETWEEN SAID AMPLIFIER OUTPUT AND EACH OF SAID INPUT MEANS, SAID FEEDBACK CIRCUITRY IN CONJUNCTION WITH SAID AMPLIFIER OUTPUT SIGNAL AND THE RESPECTIVE VOLTAGE SIGNAL SOURCES PROVIDING RESPECTIVELY AT EACH OF SAID INPUT MEANS A SUMMATION SIGNAL, EACH OF SAID VOLTAGE SIGNAL SOURCES WHOSE VALUE IS GREATER THAN A PREDETERMINED PERCENTAGE OF THE HIGHEST VOLTAGE SIGNAL COMPARED CAUSING AN INDICATIVE SUMMATION SIGNAL TO APPEAR AT ITS ASSOCIATED INPUT MEANS, AND UTILITY MEANS COUPLED TO EACH OF SAID MIXER INPUT MEANS TO BE RESPONSIVE TO AN INDICATIVE SUMMATION SIGNAL THEREAT. 